The conversion of an analog signal into a digital signal has become a conventional operation in contemporary electronic circuits, by virtue of standard commercial hardware components commonly grouped together under the acronym ADC standing for “Analog-Digital Converter”. This entails representing a signal e(t) varying in a continuous manner over time and able to take any value in a form s(t) sampled over time. Each sample can take a finite number of possible quantized values and each value is coded on a well determined number of bits. Each bit can take only two possible values, 1 or −1 for example.
Conventional ADCs offer adequate performance in terms of precision at relatively low frequencies of the input signal, of the order of a few tens or indeed hundreds of megahertz. This implies that at these frequencies, the difference between the signal represented digitally at output and the analog input signal is acceptable. But in the microwave frequency domain, when the frequency of the input signal is of the order of a few gigahertz, the dynamic range of conventional ADCs, that is to say their capacity to sample/quantize the input signal both rapidly and precisely, turns out to be markedly inadequate. Firstly, this is due to the inadequate rise time of an internal hardware component of ADCs called the sample-and-hold unit. A sample-and-hold unit has difficulty stabilizing an input signal with a view to quantizing it if its frequency is too high, the duration required for this stabilization then being too large with respect to the sampling period. This introduces errors, that is to say some digital samples may not be representative of the analog signal. Each sample can then be coded only on a reduced number of amplitude values. Intrinsically, this generates an error due to the lack of precision before the quantization of the amplitude of each sample. Consequently, the error inherent in the method of digitization of a conventional ADC at high sampling frequency is the sum of the error described, related to the insufficient speed of the sample-and-hold unit, and of the quantization rounding error which expresses the difference between the signal thus sampled-and-held and its quantized digital representation. This global error is improperly called “quantization noise” since, in practice, the part related to quantization is predominant (at least at low frequency). Thus, at high frequency the difference between the signal represented digitally at output and the analog signal at input becomes non-negligible and the precision of the ADC is no longer adequate. To summarize, the precision of conventional ADCs decreases as the frequency of the analog signal e(t) applied to their input increases. They are therefore not suited to use in applications at very high frequencies demanding good numerical precision, such as radars for example.
A method called sigma-delta modulation makes it possible to improve the precision of an ADC locally around a frequency, optionally around a high frequency. The basic principle is to arbitrarily vary the output digital signal, or to “modulate” it, so as to minimize the error for any spectral component contained in the band of interest (which depends on the use), even if some samples of the output digital signal may seem unrepresentative of the analog input signal. Accordingly, the principle of sigma-delta modulation requires that the signal be greatly over-sampled, which can only be done on a small number of bits. This amounts to increasing the temporal precision by slicing the signal into a large number of samples but, as explained above, at the price of a decrease in the precision in terms of amplitude on account of the increase in the sampling frequency. But by relying on over-sampling, the digital output signal may be modulated so as to minimize the power of this quantization noise in a determined frequency band.
In the frequency or spectral domain, it is commonly said that the Sigma-Delta modulation “shapes” the quantization noise. Indeed, the modulation of the digital output signal, which modulation is suited to the frequency of the input signal, amounts to minimizing the spectral density of the quantization noise around the frequency of the useful signal. In fact, the spectrum of the quantization noise must be “shaped” to conform to an ideal spectrum exhibiting a trough in the vicinity of the frequency of use. Thus, even if globally significant quantization noise is intrinsically generated in Sigma-Delta modulation, this being so whatever the frequency of the signal at input, at least this quantization noise is of low power in the vicinity of the frequency of use.
A Sigma-Delta modulator may be implemented on the basis of an ADC converter feedback-controlled in a conventional manner in a feedback control loop, with a view to attenuating the influence of its quantization noise on its digital output. In this case, a digital-analog converter, called a DAC converter subsequently, makes it possible to reconvert into analog the digital output signal of the ADC converter with a view to subtracting it from the input signal, based on the principle of the closed feedback control loop. An amplifier and a loop filter make it possible to circumvent the drawback of conventional ADCs by associating high frequency and fine resolution.
In addition to the phenomenon of insufficient speed observed at very high frequency of the input signal on the sample-and-hold units of an ADC converter and to which the sigma-delta modulation proposes to afford a response, a phenomenon termed “metastability” arises in respect of other hardware components of these converters, these hardware components being called comparators. Metastability is a known phenomenon of indecision in ADC converters which becomes all the more significant as the sampling frequency increases and therefore as the processing time decreases. This phenomenon has always existed, but with the increase in the operating speed of contemporary digital circuits, it has come to the fore. Because of this phenomenon, which is detailed subsequently, certain bits may not be decided on output from an ADC converter in a sigma-delta modulator: they equal neither −1 nor 1. It is then logic layers situated after the comparators of the ADC which resolve these inconclusive decisions. However, in a sigma-delta modulator, such layers are present both in the loop feedback and in the output path. These layers which are physically different therefore resolve the inconclusive decisions in a totally independent manner, on the one hand for the digital output signal and on the other hand for the digital signal returned to the input of the modulator. Thus nothing guarantees that the indecision resolutions are consistent or uniform between the digital output signal and the digital signal returned to the input. The difference between these two signals must be considered to be an added error.
Since it sends the output signal back to the input, the loop feedback digital-analog DAC converter should exhibit performance in terms of noise and linearity which is at least as good as the performance aimed at for the modulator as a whole since any spurious signal, consistent (spurious spectral lines related to linearity defects) or inconsistent (added noise, coding error), generated in the loop feedback may not be compressed by the loop.
In the subsequent description the least significant bits, also called low-order bits, will subsequently be designated by the acronym LSB standing for “Less Significant Bit”. Moreover, the most significant bits, also called high-order bits, will subsequently be designated by the acronym MSB standing for “Most Significant Bit”.
The ADC converter decoding logic possibly not being fast enough as regards the LSB bits, it may be preferable to feed back only a certain number of the MSB bits to the loop feedback DAC converter.
In this case, a digital signal whose MSB bits, on the one hand, are supposed to represent the fed back signal for which the quantization noise is shaped by the loop and whose LSB bits, on the other hand, represent a coding of the quantization noise not shaped by the loop, which coding exhibits its own quantization noise, is available at the modulator output. Indeed the ADC converter may be considered to be a linear system which adds noise, that is to say the quantization noise. The output of the ADC converter, on NMSB+NLSB bits in total, comprises NMSB MSB bits which are fed back in the DAC converter and NLSB LSB bits which are not. The NMSB MSB bits therefore carry the useful signal accompanied by the low-resolution quantization noise bMSB shaped by the loop. The NLSB LSB bits provide noise corresponding to the unshaped difference bLSB−bMSB between the high- and low-resolution quantization noise bMSB and bLSB.
A possible improvement aimed at limiting the errors related to metastability problems is to re-sample the output of the loop feedback DAC converter with a second ADC so as to have available a second more accurate item of information on the signal actually fed back. In this respect the output of novel ADC will be considered to be the main output of the modulator and that of the loop ADC as the secondary output. The discrepancy between the main signal and the MSB bits of the secondary signal is, with respect to the LSB bits, a complementary measure of the noise not reshaped by the loop. It is therefore possible to consider that the secondary output carries the sum of the main signal, of its shaped quantization noise, of the opposite of the unshaped quantization noise, of the quantization noise bLSB and of the metastability noise. The sum of these last two contributions may be interpreted as the error in estimating the quantization noise not shaped by the system. If the response of the loop is known with sufficient precision it is then possible to take account of the additional item of information carried by the secondary signal (unshaped quantization noise coded with a residual error) so as to numerically improve the resolution of the modulator.
One possibility for thus improving the resolution on the basis of a measurement of the error of the modulator is described in the publication by T. C. Leslie and B. Singh entitled An improved ΣΔ modulator architecture, IEEE Proc. ISCAS'90, vat pp. 372-375, May 1990. Other implementations are also described in different ways in the book Delta-Sigma Data Converters, IEEE Press, Ed. Norsworthy, Schreier & Temes, Ch 8, pp. 273-275 and in U.S. Pat. No. 5,838,272 entitled Error correcting sigma-delta modulation decoding. These publications show that in a general manner, anywhere in the modulator and in the coding chain, the signal present can be written as a linear combination of the signal and of an error whose coefficients depend on the frequency. It is therefore possible by appropriate filtering and addition to correct the error at output.
When the working frequency is very high, these processings become difficult to carry out on account of their complexity since they are customarily performed before the decimation operation. It is therefore necessary to find solutions making it possible to improve the resolution of sigma-delta modulators operating at high frequency without however overburdening the processing architecture in an ill-considered manner.